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Section II. HardCopy APEX Device Family Data Sheet This section provides designers with the data sheet specifications for HardCopy(R) APEXTM devices. These chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for HardCopy APEX devices. This section contains the following: Chapter 7, Introduction to HardCopy APEX Devices Chapter 8, Description, Architecture, and Features Chapter 9, Boundary-Scan Support Chapter 10, Operating Conditions Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section II-1 Preliminary Revision History HardCopy Series Handbook, Volume 1 Section II-2 Preliminary Altera Corporation 7. Introduction to HardCopy APEX Devices H51006-2.3 Introduction HardCopy(R) APEXTM devices enable high-density APEX 20KE device technology to be used in high-volume applications where significant cost reduction is desired. HardCopy APEX devices are physically and functionally compatible with APEX 20KC and APEX 20KE devices. They combine the time-to-market advantage, performance, and flexibility of APEX 20KE devices with the ability to move to high-volume, low-cost devices for production. The migration process from an APEX 20KE device to a HardCopy APEX device is fully automated, with designer involvement limited to providing a few Quartus(R) II software-generated output files. HardCopy APEX devices are manufactured using an 0.18-m CMOS six-layer-metal process technology: Features... Preserves functionality of a configured APEX 20KC or APEX 20KE device Pin-compatible with APEX 20KC or APEX 20KE devices Meets or exceeds timing of configured APEX 20KE and APEX 20KC devices Optional emulation of original programmable logic device (PLD) programming sequence High-performance, low-power device MultiCore architecture integrating embedded memory and look-up table (LUT) logic used for register-intensive functions Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM) Customization performed through metallization layers Altera Corporation September 2008 7-1 HardCopy Series Handbook, Volume 1 High-density architecture: 400,000 to 1.5 million typical gates (Table 7-1) Up to 51,840 logic elements (LEs) Up to 442,368 RAM bits that can be used without reducing available logic Table 7-1. HardCopy APEX Device Features Feature Maximum system gates Typical gates LEs ESBs Maximum RAM bits Phase-locked loops (PLLs) Maximum macrocells Maximum user I/O pins Note to Table 7-1: (1) Note (1) HC20K600 1,537,000 600,000 24,320 152 311,296 4 2,432 588 HC20K400 1,052,000 400,000 16,640 104 212,992 4 1,664 488 HC20K1000 1,772,000 1,000,000 38,400 160 327,680 4 2,560 708 HC20K1500 2,392,000 1,500,000 51,840 216 442,368 4 3,456 808 The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 57,000 additional gates. ...and More Features Low-power operation: 1.8-V supply voltage (Table 7-2) MultiVolt I/O support for 1.8-, 2.5-, and 3.3-V interfaces ESBs offering power-saving mode Flexible clock management circuitry with up to four phase-locked loops (PLLs): Built-in low-skew clock tree Up to eight global clock signals ClockLock feature reducing clock delay and skew ClockBoost feature providing clock multiplication and division ClockShift feature providing clock phase and delay shifting Powerful I/O features: Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits 7-2 Altera Corporation September 2008 ...and More Features Support for high-speed external memories, including double-data rate (DDR), synchronous dynamic RAM (SDRAM), and zero-bus-turnaround (ZBT) static RAM (SRAM) 16 input and 16 output LVDS channels Fast tCO and tSU times for complex logic MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces Individual tri-state output enable control for each pin Output slew-rate control to reduce switching noise Support for advanced I/O standards, including LVDS, LVPECL, PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I Supports hot-socketing operation Table 7-2. HardCopy APEX Device Supply Voltages Feature Internal supply voltage (VCCINT) MultiVolt I/O interface voltage levels (VCCIO) Note to Table 7-2: (1) HardCopy APEX devices can be 5.0-V tolerant by using an external resistor. Voltage 1.8 V 1.8 V, 2.5 V, 3.3 V, 5.0 V (1) HardCopy APEX device implementation features: Customized interconnect for each design HardCopy APEX devices preserve APEX 20K device MegaLAB structure, LEs, ESBs, I/O element (IOE), PLLs, and LVDS circuitry Up to four metal layers customizable for customer designs Completely automated proprietary design migration flow Testability analysis and fix Automatic test pattern generation (ATPG) Automatic place and route Static timing analysis Static functional verification Physical verification Altera Corporation September 2008 7-3 HardCopy Series Handbook, Volume 1 Tables 7-3 through 7-6 show the HardCopy APEX device ball-grid array (BGA) and FineLine BGA package options, I/O counts, and sizes. Table 7-3. HardCopy APEX Device BGA Package Options and I/O Count Note (1) Device HC20K400 HC20K600 HC20K1000 HC20K1500 652-Pin BGA 488 488 488 488 Table 7-4. HardCopy APEX Device FineLine BGA Package Options and I/O Count Note (1) Device HC20K400 HC20K600 HC20K1000 HC20K1500 Note to Tables 7-3 and 7-4: (1) I/O counts include dedicated input and clock pins. 672-Pin 488 508 508 - 1,020-Pin - 588 708 808 Table 7-5. HardCopy APEX Device BGA Package Sizes Feature Pitch (mm) Area (mm2) Length x width (mm x mm) 652-Pin BGA 1.27 2,025 45.0 x 45.0 Table 7-6. HardCopy APEX Device FineLine BGA Package Sizes Feature Pitch (mm) Area (mm2) Length x width (mm x mm) 672-Pin 1.00 729 27 x 27 1,020-Pin 1.00 1,089 33 x 33 7-4 Altera Corporation September 2008 Document Revision History Document Revision History Table 7-7 shows the revision history for this chapter. Table 7-7. Document Revision History Date and Document Version September 2008, v2.3 June 2007, v2.2 December 2006 v2.1 March 2006 January 2005 v2.0 June 2003 v1.0 Changes Made Updated chapter number and metadata. Minor text edits. Updated revision history. Formerly chapter 9; no content change. Update device names and other minor textual changes Initial release of Chapter 9, Introduction to HardCopy APEX Devices, in the HardCopy Device Handbook Summary of Changes -- -- -- -- -- -- Altera Corporation September 2008 7-5 HardCopy Series Handbook, Volume 1 7-6 Altera Corporation September 2008 8. Description, Architecture, and Features H51007-2.3 Introduction HardCopy(R) APEXTM devices extend the flexibility of high-density FPGAs to a cost-effective, high-volume production solution. The migration process from an Altera(R) FPGA to a HardCopy APEX device offers seamless migration of a high-density system-on-a-programmable-chip (SOPC) design to a low-cost alternative device with minimal risk. Using HardCopy APEX devices, Altera's SOPC solutions can be leveraged from prototype to production, while reducing costs and speeding time-to-market. A significant benefit of HardCopy devices is that customers do not need to be involved in the device migration process. Unlike application-specific integrated circuit (ASIC) development, the HardCopy design flow does not require generation of test benches, test vectors, or timing and functional simulation. The HardCopy migration process only requires the Quartus(R) II software-generated output files from a fully functional APEX 20KE or APEX 20KC device. Altera performs the migration and delivers functional prototypes in as few as seven weeks. A risk-free alternative to ASICs, HardCopy APEX devices are customizable, full-featured devices created by Altera's proprietary design migration methodology. They are based on Altera's industry-leading high-density device architecture and use an area-efficient sea-of-logic-elements (SOLE) core. HardCopy APEX devices retain all the same features as the APEX 20KE and APEX 20KC devices, which combine the strength of LUT-based and product-term-based devices in conjunction with the same embedded memory structures. All routing resources that were programmable in the APEX 20K device family are replaced by custom interconnect, resulting in a considerable die size reduction and subsequent cost saving. The SRAM configuration cells of the original FPGA are replaced in HardCopy APEX devices by metal elements, which define the function of each logic element (LE), embedded memory, and I/O cell in the device. These resources are connected to each other using the same metallization layers. Once a HardCopy APEX device has been manufactured, the functionality of the device is fixed and no programming is possible. Altera performs the migration of the original FPGA design to an equivalent HardCopy APEX device using a proprietary design migration flow. Altera Corporation September 2008 8-1 HardCopy Series Handbook, Volume 1 The migration of a FPGA to a HardCopy APEX device begins with a user design that has been implemented in an APEX 20KE or APEX 20KC device. Table 8-1 shows the device equivalence for HardCopy and APEX 20KE or APEX 20KC devices. Table 8-1. HardCopy and APEX 20KE or APEX 20C Device Equivalence HardCopy APEX Device HC20K1500 HC20K1000 HC20K600 HC20K400 APEX 20KE Device EP20K1500E EP20K1000E EP20K600E EP20K400E APEX 20KC Device EP20K1500C EP20K1000C EP20K600C EP20K400C 1 To ensure HardCopy device performance and functionality, the APEX 20K design must be completely debugged before committing the design to HardCopy device migration. HardCopy APEX device implementation begins with extracting the Quartus II software-generated SRAM Object File (.sof) and converting its connectivity information into a structural Verilog HDL netlist. This netlist is then placed and routed in a similar fashion to a gate array. There are no dedicated routing channels. The router can exploit all available metal layers (up to four) and route over LE cells and other functional blocks. Altera's proprietary architecture and design methodology will guarantee virtually 100% routing of any APEX 20KE or APEX 20KC design compiled and fitted successfully using the Quartus II software. Place and route is timing-driven and will comply with the timing constraints of the original FPGA design as specified in the Quartus II software. Figure 8-1 shows a diagram of the HardCopy APEX device architecture. 8-2 Altera Corporation September 2008 Introduction Figure 8-1. HardCopy APEX Device Architecture LE LAB I/O Elements ESB Strip of auxiliary gates (SOAG) PLLs The strip of auxiliary gates (SOAG) is an Altera proprietary feature designed into the HardCopy APEX device and is used during the HardCopy device implementation process. The SOAG structures can be configured into several different types of functions through the use of metallization. For example, high fanout signals require adequate buffering, so buffers are built out of SOAG cells for this purpose. HardCopy APEX devices include the same advanced features as the APEX 20KE and APEX 20KC devices, such as enhanced I/O standard support, content-addressable memory (CAM), additional global clocks, and enhanced ClockLock circuitry. Table 8-2 lists the features included in HardCopy APEX devices. Table 8-2. HardCopy APEX Device Features (Part 1 of 2) Feature MultiCore system integration Hot-socketing support 32-/64-bit, 33-MHz PCI 32-/64-bit, 66-MHz PCI MultiVolt I/O operation Full support Full support Full compliance Full compliance 1.8-V, 2.5-V, or 3.3-V VCCIO VCCIO selected bank by bank 5.0-V tolerant with use of external resistor HardCopy Devices Altera Corporation September 2008 8-3 HardCopy Series Handbook, Volume 1 Table 8-2. HardCopy APEX Device Features (Part 2 of 2) Feature ClockLock support HardCopy Devices Clock delay reduction m /(n x v) clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift circuitry LVDS support Up to four PLLs ClockShift, clock phase adjustment Dedicated clock and input pins Eight I/O standard support 1.8-V, 2.5-V, 3.3-V, 5.0-V I/O 3.3-V PCI and PCI-X 3.3-V AGP CTT GTL+ LVCMOS LVTTL True-LVDS and LVPECL data pins LVDS and LVPECL clock pins HSTL class I PCI-X SSTL-2 class I and II SSTL-3 class I and II CAM Dual-port RAM FIFO RAM ROM Memory support All HardCopy APEX devices are tested using automatic test pattern generation (ATPG) vectors prior to shipment. For fully synchronous designs near 100%, fault coverage can be achieved through the built-in full-scan architecture. ATPG vectors allow the designer to focus on simulation and design verification. Because the configuration of HardCopy APEX devices is built-in during manufacture, they cannot be configured in-system. However, if the APEX 20KE or APEC 20KC device configuration sequence must be emulated, the HardCopy APEX device has this capability. f All of the device features of APEX 20KE and APEX 20KC devices are available in HardCopy APEX devices. For a detailed description of these device features, refer to the APEX 20K Programmable Logic Device Family Data Sheet and the APEX 20KC Programmable Logic Device Family Data Sheet. 8-4 Altera Corporation September 2008 Differences Between HardCopy APEX and APEX 20K FPGAs Differences Between HardCopy APEX and APEX 20K FPGAs Several differences must be considered before a design is ready for implementation in HardCopy technology: HardCopy APEX devices are only customizable at the time they are manufactured. Make sure that the original APEX 20KE or APEX 20KC device has undergone thorough testing in the end-system before deciding to proceed with migration to a HardCopy APEX device, because no changes can be made to the HardCopy APEX device after it has been manufactured. ESBs that are configured as RAM or CAM will power-up un-initialized in the HardCopy APEX device. In the FPGA it is possible to configure, or "pre-load," the ESB memory as part of the configuration sequence, then overwrite it when the device is in normal functional mode. This pre-loaded memory feature of the FPGA is not available in HardCopy devices. If a design contains RAM or CAM with assumed data values at power-up, then the HardCopy APEX device will not operate as expected. If a design uses this feature, it should be re-compiled without the memory pre-load. ESBs configured as ROM are fully supported. The JTAG boundary scan order in the HardCopy APEX device is different compared to the APEX 20K device. A HardCopy BSDL file that describes the re-ordered boundary scan chain should be used. 1 The BSDL files for HardCopy APEX devices are different from the corresponding APEX 20KE or APEX 20KC devices. Download the correct HardCopy BSDL file from Altera's website at www.altera.com. The advanced 0.18-m aluminum metal process is used to support both APEX 20KE and APEX 20KC devices. The performance improvement achieved by the die size reduction and metal interconnect optimization more than offsets the need for copper in this case. Altera guarantees that a target HardCopy APEX device will provide the same or better performance as in the corresponding APEX 20KE or APEX 20KC device. Power-up Mode and Configuration Emulation Unlike their FPGA counterparts, HardCopy APEX devices do not need to be configured. However, to facilitate seamless migration, configuration can be emulated in these devices. There are three modes in which a Altera Corporation September 2008 8-5 HardCopy Series Handbook, Volume 1 HardCopy APEX device can be prepared for operation after power up: instant on, instant on after 50 ms, and configuration emulation. Each mode is described below. In instant on mode, the HardCopy APEX device is available for use shortly after the device receives power. The on-chip power-on-reset (POR) circuit will set or reset all registers. The CONF_DONE output will be tri-stated once the power-on reset has elapsed. No configuration device or configuration input signals are necessary. In instant on after 50 ms mode, the HardCopy APEX device performs in a similar fashion to the Instant On mode, except that there is an additional delay of 50 ms (nominal), during which time the device is held in reset stage. The CONF_DONE output is pulled low during this time and then tri-stated after the 50 ms have elapsed. No configuration devices or configuration input signals are necessary for this option. In configuration emulation mode, the HardCopy APEX device undergoes an emulation of a full configuration sequence as if configured by an external processor or an EPC device. In this mode, the CONF_DONE signal is tri-stated after the correct number of clock cycles. This mode may be useful where there is some dependency on the configuration sequence (for example, multi-device configuration or processor initialization). In this mode, the device expects to see all configuration control and data input signals. Speed Grades Because HardCopy APEX devices are customized, no speed grading is performed. All HardCopy APEX devices will meet the timing requirements of the original FPGA of the fastest speed grade. Generally, HardCopy APEX devices will have a higher fMAX than the corresponding FPGA, but the speed increase will vary on a design-by-design basis. The HardCopy migration process requires several Quartus II software-generated files. These key output files are listed and explained below. Quartus IIGenerated Output Files The SRAM Object File (.sof) contains all of the necessary information needed to configure a FPGA The Compiler Report File (.csf.rpt) is parsed to extract useful information about the design The Verilog atom-based netlist file (.vo) is used to check the HardCopy netlist The pin out information file (.pin) contains user signal names and I/O configuration information 8-6 Altera Corporation September 2008 Document Revision History The Delay Information File (.sdo) is used to check the original FPGA timing A completed HardCopy timing requirements file describes all necessary timing information on the design. A template of this text file is available for download from the Altera website at www.altera.com. The migration process consists of several steps. First, a netlist is constructed from the SOF. Then, the netlist is checked to ensure that the built-in scan test structures will operate correctly. The netlist is then fed into a place-and-route engine, and the design interconnect is generated. Static timing analysis ensures that all timing constraints are met, and static functional verification techniques are employed to ensure correct device migration. After successfully completing these stages, physical verification of the device takes place, and the metal mask layers are taped out to fabricate HardCopy APEX devices. Document Revision History Table 8-3 shows the revision history for this chapter. Table 8-3. Document Revision History Date and Document Version September 2008, v2.3 June 2007, v2.2 December 2006 v2.1 March 2006 January 2005 v2.0 June 2003 v1.0 Changes Made Updated chapter number and metadata. Minor text edits. Updated revision history. Formerly chapter 10; no content change. Update device names and other minor textual changes Initial release of Chapter 10, Description, Architecture and Features, in the HardCopy Device Handbook Summary of Changes -- -- -- -- -- -- Altera Corporation September 2008 8-7 HardCopy Series Handbook, Volume 1 8-8 Altera Corporation September 2008 9. Boundary-Scan Support H51009-2.3 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support All HardCopy devices provide JTAG boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. HardCopy(R) APEXTM devices support the JTAG instructions shown in Table 9-1. 1 The BSDL files for HardCopy devices are different from the corresponding APEX 20KE or APEX 20KC parts. Download the correct HardCopy BSDL file from Altera's website at www.altera.com. Table 9-1. HardCopy APEX JTAG Instructions JTAG Instruction SAMPLE/PRELOAD Description SAMPLE/PRELOAD allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. It is also used by the SignalTap(R) embedded logic analyzer. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO. EXTEST BYPASS USERCODE IDCODE HardCopy APEX devices instruction register length is 10 bits; the USERCODE register length is 32 bits. Tables 9-2 and 9-3 show the boundary-scan register length and device IDCODE information for HardCopy devices. Altera Corporation September 2008 9-1 HardCopy Series Handbook, Volume 1 Table 9-2. HardCopy APEX Boundary-Scan Register Length Device HC20K400 HC20K600 HC20K1000 HC20K1500 Boundary-Scan Register Length 1,506 1,806 2,190 2,502 Table 9-3. 32-Bit HardCopy APEX Device IDCODE IDCODE (32 Bits) Note (1) Device Version (4 Bits) 0000 0000 0000 0000 Part Number (16 Bits) 1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000 1001 0101 0000 0000 Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 1 (1 Bit) (2) 1 1 1 1 HC20K400 HC20K600 HC20K1000 HC20K1500 Notes to Table 9-3: (1) (2) The most significant bit (MSB) is on the left. The IDCODE's least significant bit (LSB) is always 1. Figure 9-1 shows the timing requirements for the JTAG signals. Figure 9-1. HardCopy JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ 9-2 Altera Corporation September 2008 Document Revision History Table 9-4 shows the JTAG timing parameters and values for HardCopy devices. Table 9-4. HardCopy APEX JTAG Timing Parameters and Values Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 20 45 35 35 35 ns ns ns ns ns ns ns ns f For more information about using JTAG BST circuitry in Altera devices, refer to Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices. Table 9-5 shows the revision history for this chapter. Document Revision History Table 9-5. Document Revision History (Part 1 of 2) Date and Document Version September 2008, v2.3 June 2007, v2.2 December 2006 v2.1 March 2006 Changes Made Updated chapter number and metadata. Minor text edits. Updated revision history. Formerly chapter 11; no content change. Summary of Changes -- -- Updated revision history. Altera Corporation September 2008 9-3 HardCopy Series Handbook, Volume 1 Table 9-5. Document Revision History (Part 2 of 2) Date and Document Version January 2005 v2.0 June 2003 v1.0 Changes Made Update device names and other minor textual changes. Initial release of Boundary-Scan Support in the HardCopy Device Handbook. Summary of Changes -- -- 9-4 Altera Corporation September 2008 10. Operating Conditions H51010-2.3 Recommended Operating Conditions Tables 10-1 through 10-4 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 1.8-V HardCopy (R) APEXTM devices. Table 10-1. HardCopy APEX Device Absolute Maximum Ratings Note (1) Symbol V CCINT V CCIO VI I OUT T STG TAMB TJ DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias BGA packages, under bias Parameter Supply voltage Conditions With respect to ground (2) Min -0.5 -0.5 -0.5 -25 -65 -65 Max 2.5 4.6 4.6 25 150 135 135 Unit V V V mA C C C Table 10-2. HardCopy APEX Device Recommended Operating Conditions Symbol V CCINT V CCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation (3), (4) (3), (4) (3), (4) (2), (5) Conditions Min 1.71 (1.71) 3.00 (3.00) 2.375 (2.375) -0.5 0 Max 1.89 (1.89) 3.60 (3.60) 2.625 (2.625) 4.1 V CCIO 85 100 40 40 Unit V V V V V C C ns ns VI VO TJ tR tF Input voltage Output voltage Junction temperature For commercial use For industrial use 0 -40 Input rise time (10% to 90%) Input fall time (90% to 10%) Altera Corporation September 2008 10-1 HardCopy Series Handbook, Volume 1 Table 10-3. HardCopy APEX Device DC Operating Conditions (Part 1 of 2) Notes (6), (7), (8) Symbol V IH V IL V OH Parameter High-level LVTTL, CMOS, or 3.3-V PCI input voltage Low-level LVTTL, CMOS, or 3.3-V PCI input voltage Conditions Min 1.7, 0.5 x VCCIO (8) -0.5 2.4 V CCIO - 0.2 0.9 x VCCIO Typ Max 4.1 0.8, 0.3 x VCCIO (8) Unit V V V V V 3.3-V high-level LVTTL output I OH = -12 mA DC, voltage V CCIO = 3.00 V (9) 3.3-V high-level LVCMOS output voltage 3.3-V high-level PCI output voltage 2.5-V high-level output voltage I OH = -0.1 mA DC, V CCIO = 3.00 V (9) I OH = -0.5 mA DC, V CCIO = 3.00 to 3.60 V (9) I OH = -0.1 mA DC, V CCIO = 2.30 V (9) I OH = -1 mA DC, V CCIO = 2.30 V (9) I OH = -2 mA DC, V CCIO = 2.30 V (9) 2.1 2.0 1.7 0.4 0.2 0.1 x VCCIO V V V V V V V OL 3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage 3.3-V low-level PCI output voltage I OL = 12 mA DC, V CCIO = 3.00 V (10) I OL = 0.1 mA DC, V CCIO = 3.00 V (10) I OL = 1.5 mA DC, V CCIO = 3.00 to 3.60 V (10) 2.5-V low-level output voltage I OL = 0.1 mA DC, V CCIO = 2.30 V (10) I OL = 1 mA DC, V CCIO = 2.30 V (10) I OL = 2 mA DC, V CCIO = 2.30 V (10) II I OZ I CC0 Input pin leakage current (11) Tri-stated I/O pin leakage current (11) V CC supply current (standby) (All ESBs in power-down mode) V I = 4.1 to -0.5 V VO = 4.1 to -0.5 V V I = ground, no load, no toggling inputs, -7 speed grade V I = ground, no load, no toggling inputs, -8, -9 speed grades -10 -10 10 0.2 0.4 0.7 10 10 V V V A A mA 5 mA 10-2 Altera Corporation September 2008 Recommended Operating Conditions Table 10-3. HardCopy APEX Device DC Operating Conditions (Part 2 of 2) Notes (6), (7), (8) Symbol R CONF Parameter Value of I/O pin pull-up resistor before and during configuration emulation Conditions V CCIO = 3.0 V (12) V CCIO = 2.375 V (12) V CCIO = 1.71 V (12) Min 20 30 60 Typ Max 50 80 150 Unit k k k Table 10-4. HardCopy APEX Device Capacitance Note (13) Symbol CIN CINCLK COUT (1) (2) (3) (4) (5) (6) (7) (8) (9) Parameter Input capacitance Input capacitance on dedicated clock pin Output capacitance Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Min Typ 8 12 8 Max pF pF pF Notes to Table 10-1 through 10-4: Refer to the Operating Requirements for Altera Devices Data Sheet. Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -0.5 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. Numbers in parentheses are for industrial-temperature-range devices. Maximum VCC rise time is 100 ms, and VCC must rise monotonically. All pins (including dedicated inputs, clock, I/O, and JTAG pins) may be driven before VCCINT and VCCIO are powered. Typical values are for T A = 25 C, V CCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V, or 3.3 V. These values are specified under the HardCopy device recommended operating conditions, as shown in Table 10-2 on page 10-1. Refer to AN 117: Using Selectable I/O Standards in Altera Devices for the VIH , VIL , VOH , VOL , and I I parameters when VCCIO = 1.8 V. The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP, SSTL-2, SSTL-3, and HSTL. The IOH parameter refers to high-level TTL, PCI, or CMOS output current. This value is specified for normal device operation. The value may vary during power-up. Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO . Capacitance is sample-tested only. (10) (11) (12) (13) Altera Corporation September 2008 10-3 HardCopy Series Handbook, Volume 1 Tables 10-5 through 10-20 list the DC operating specifications for the supported I/O standards. These tables list minimal specifications only; HardCopy devices may exceed these specifications. Table 10-5. LVTTL I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 2.0 -0.3 Maximum 3.6 VCCIO + 0.3 0.8 10 Units V V V A V VIN = 0 V or 3.3 V IOH = -12 mA, VCCIO = 3.0 V (1) IOL = 12 mA, VCCIO = 3.0 V (2) -10 2.4 0.4 V Table 10-6. LVCMOS I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Power supply voltage range High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 3.0 2.0 -0.3 Maximum 3.6 VCCIO + 0.3 0.8 10 Units V V V A V VIN = 0 V or 3.3 V VCCIO = 3.0 V IOH = -0.1 mA (1) VCCIO = 3.0 V IOL = 0.1 mA (2) -10 VCCIO - 0.2 0.2 V 10-4 Altera Corporation September 2008 Recommended Operating Conditions Table 10-7. 2.5-V I/O Specifications Symbol VCCIO VIH VIL II VOH Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Conditions Minimum 2.375 1.7 -0.3 Maximum 2.625 VCCIO + 0.3 0.7 10 Units V V V A V V V VIN = 0 V or 3.3 V IOH = -0.1 mA (1) IOH = -1 mA (1) IOH = -2 mA (1) -10 2.1 2.0 1.7 VOL Low-level output voltage IOL = 0.1 mA (2) IOL = 1 mA (2) IOL = 2 mA (2) 0.2 0.4 0.7 V V V Table 10-8. 1.8-V I/O Specifications Symbol VCCIO VIH VIL II VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum 1.7 0.65 x VCCIO Maximum 1.9 VCCIO + 0.3 0.35 x VCCIO Units V V V A V VIN = 0 V or 3.3 V IOH = -2 mA (1) IOL = 2 mA (2) -10 VCCIO - 0.45 10 0.45 V Table 10-9. 3.3-V PCI Specifications (Part 1 of 2) Symbol VCCIO VIH Parameter I/O supply voltage High-level input voltage Conditions Minimum 3.0 0.5 x VCCIO Typical 3.3 Maximum 3.6 VCCIO + 0.5 Units V V Altera Corporation September 2008 10-5 HardCopy Series Handbook, Volume 1 Table 10-9. 3.3-V PCI Specifications (Part 2 of 2) Symbol VIL II VOH VOL Parameter Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum -0.5 Typical Maximum 0.3 x VCCIO 10 Units V A V 0 < VIN < VCCIO IOUT = -500 A IOUT = 1,500 A -10 0.9 x VCCIO 0.1 x VCCIO V Table 10-10. 3.3-V PCI-X Specifications Symbol VCCIO VIH VIL VIPU IIL VOH VOL LPIN Parameter Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input pin leakage current High-level output voltage Low-level output voltage Pin Inductance Conditions Minimum 3.0 0.5 x VCCIO -0.5 0.7 x VCCIO Typical 3.3 Maximum 3.6 VCCIO + 0.5 0.35 x VCCIO Units V V V V 0 < VIN < VCCIO IOUT = -500 A IOUT = 1500 A -10.0 0.9 x VCCIO 10.0 V 0.1 x VCCIO 15.0 V nH Table 10-11. 3.3-V LVDS I/O Specifications (Part 1 of 2) Symbol VCCIO VOD VOD Parameter I/O supply voltage Differential output voltage Change in VOD between high and low Conditions RL = 100 RL = 100 Minimum 3.135 250 Typical 3.3 Maximum 3.465 450 50 Units V mV mV VOS Output offset voltage RL = 100 1.125 1.25 1.375 V 10-6 Altera Corporation September 2008 Recommended Operating Conditions Table 10-11. 3.3-V LVDS I/O Specifications (Part 2 of 2) Symbol VOS Parameter Change in VOS between high and low Differential input threshold Receiver input voltage range Receiver differential input resistor (external to APEX 20K devices) Conditions RL = 100 Minimum Typical Maximum 50 Units mV VTH VIN RL VCM = 1.2 V -100 0.0 90 100 100 2.4 110 mV V Table 10-12. GTL+ I/O Specifications Symbol VTT VREF VIH Parameter Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage Conditions Minimum 1.35 0.88 VREF + 0.1 Typical 1.5 1.0 Maximum 1.65 1.12 Units V V V VIL VREF - 0.1 V VOL IOL = 36 mA (2) 0.65 V Table 10-13. SSTL-2 Class I Specifications (Part 1 of 2) Symbol VCCIO VTT VREF VIH VIL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage Conditions Minimum 2.375 VREF - 0.04 1.15 VREF + 0.18 -0.3 Typical 2.5 VREF 1.25 Maximum 2.625 VREF + 0.04 1.35 VCCIO + 0.3 VREF - 0.18 Units V V V V V Altera Corporation September 2008 10-7 HardCopy Series Handbook, Volume 1 Table 10-13. SSTL-2 Class I Specifications (Part 2 of 2) Symbol VOH VOL Parameter High-level output voltage Low-level output voltage Conditions IOH = -7.6 mA (1) IOL = 7.6 mA (2) Minimum VTT + 0.57 Typical Maximum Units V VTT - 0.57 V Table 10-14. SSTL-2 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 2.375 VREF - 0.04 1.15 VREF + 0.18 -0.3 Typical 2.5 VREF 1.25 Maximum 2.625 VREF + 0.04 1.35 VCCIO + 0.3 VREF - 0.18 Units V V V V V V IOH = -15.2 mA (1) IOL = 15.2 mA (2) VTT + 0.76 VTT - 0.76 V Table 10-15. SSTL-3 Class I Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3 Typical 3.3 VREF 1.5 Maximum 3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2 Units V V V V V V IOH = -8 mA (1) IOL = 8 mA (2) VTT + 0.6 VTT - 0.6 V 10-8 Altera Corporation September 2008 Recommended Operating Conditions Table 10-16. SSTL-3 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3 Typical 3.3 VREF 1.5 Maximum 3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2 Units V V V V V V IOH = -16 mA (1) IOL = 16 mA (2) VTT + 0.8 VTT - 0.8 V Table 10-17. HSTL Class I I/O Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter I/O supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 1.71 VREF - 0.05 0.68 VREF + 0.1 -0.3 Typical 1.8 VREF 0.75 Maximum 1.89 VREF + 0.05 0.90 VCCIO + 0.3 VREF - 0.1 Units V V V V V V IOH = -8 mA (1) IOL = 8 mA (2) VCCIO - 0.4 0.4 V Table 10-18. LVPECL Specifications (Part 1 of 2) Symbol VCCIO VIH VIL VOH Parameter Output Supply Voltage Low-level input voltage High-level input voltage Low-level output voltage Minimum 3.135 1,300 2,100 1,450 Typical 3.3 Maximum 3.465 1,700 2,600 1,650 Units V mV mV mV Altera Corporation September 2008 10-9 HardCopy Series Handbook, Volume 1 Table 10-18. LVPECL Specifications (Part 2 of 2) Symbol VOL VID VOD tr, t f tDSKEW tO RL Parameter High-level output voltage Input voltage differential Output voltage differential Rise and fall time (20 to 80%) Differential skew Output load Receiver differential input resistor Minimum 2,275 400 625 85 Typical Maximum 2,420 Units mV mV mV ps ps 600 800 950 950 325 25 150 100 Table 10-19. 3.3-V AGP I/O Specifications Symbol VCCIO VREF VIH VIL VOH VOL II Parameter I/O supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input pin leakage current Conditions Minimum 3.15 0.39 x VCCIO 0.5 x VCCIO Typical 3.3 Maximum 3.45 0.41 x VCCIO VCCIO + 0.5 0.3 x VCCIO Units V V V V V V I OUT = -500 A I OUT = 1500 A 0 < VIN < VCCIO 0.9 x VCCIO 3.6 0.1 x VCCIO -10 10 Table 10-20. CTT I/O Specifications (Part 1 of 2) Symbol VCCIO VTT/VREF (3) VIH Parameter I/O supply voltage Termination and reference voltage High-level input voltage Conditions Minimum 3.0 1.35 VREF + 0.2 Typical 3.3 1.5 Maximum 3.6 1.65 Units V V V 10-10 Altera Corporation September 2008 Recommended Operating Conditions Table 10-20. CTT I/O Specifications (Part 2 of 2) Symbol VIL II VOH VOL IO Parameter Low-level input voltage Input pin leakage current High-level output voltage Low-level output voltage Conditions Minimum Typical Maximum VREF - 0.2 Units V A V 0 < VIN < VCCIO IOH = -8 mA (1) IOL = 8 mA (2) -10 VREF + 0.4 10 VREF - 0.4 -10 10 V A Output leakage GND VOUT VCCIO current (when output is high Z) Notes to Tables 10-5 through 10-20: (1) (2) (3) The IOH parameter refers to high-level output current. The I OL parameter refers to low-level output current. This parameter applies to open-drain pins as well as output pins. VREF specifies center point of switching range. Altera Corporation September 2008 10-11 HardCopy Series Handbook, Volume 1 Figure 10-1 shows the output drive characteristics of HardCopy APEX devices. Figure 10-1. Output Drive Characteristics of HardCopy APEX Devices 120 110 100 90 80 Typical IO 70 Output Current (mA) 60 50 40 30 20 10 0.5 1 1.5 2 2.5 3 IOH VCCINT = 1.8 V VCCIO = 3.3 V Room Temperature IOL 60 55 50 45 40 Typical IO 35 Output Current (mA) 30 25 20 15 10 5 0.5 1 1.5 2 2.5 3 IOL VCCINT = 1.8 V VCCIO = 2.5V Room Temperature IOH Vo Output Voltage (V) Vo Output Voltage (V) 26 24 22 20 18 Typical IO 16 Output Current (mA) 14 12 10 8 6 4 2 0.5 1 1.5 2.0 IOH VCCINT = 1.8V VCCIO = 1.8V Room Temperature IOL Vo Output Voltage (V) 10-12 Altera Corporation September 2008 Recommended Operating Conditions Figure 10-2 shows the timing model for bidirectional I/O pin timing. Figure 10-2. Synchronous Bidirectional Pin External Timing OE Register Dedicated Clock D PRN Q t XZBIDIR t ZXBIDIR tOUTCOBIDIR Bidirectional Pin CLRN Output IOE Register PRN D Q CLRN IOE Register tINSUBIDIR tINHBIDIR Input Register D PRN Q CLRN Tables 10-21 and 10-22 describe HardCopy APEX device external timing parameters. Table 10-21. HardCopy APEX Device External Timing Parameters Note (1) Symbol tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL Clock Parameter Setup time with global clock at IOE register Hold time with global clock at IOE register Clock-to-output delay with global clock at IOE output register Setup time with PLL clock at IOE input register Hold time with PLL clock at IOE input register Clock-to-output delay with PLL clock at IOE output register Conditions C1 = 35 pF C1 = 35 pF Table 10-22. HardCopy APEX Device External Bidirectional Timing Parameters (Part 1 of 2) Note (1) Symbol tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR Parameter Setup time for bidirectional pins with global clock at LAB-adjacent input register Hold time for bidirectional pins with global clock at LAB-adjacent input register Clock-to-output delay for bidirectional pins with global clock at IOE register Synchronous output enable register to output buffer disable delay Condition C1 = 35 pF C1 = 35 pF Altera Corporation September 2008 10-13 HardCopy Series Handbook, Volume 1 Table 10-22. HardCopy APEX Device External Bidirectional Timing Parameters (Part 2 of 2) Note (1) Symbol tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL Parameter Synchronous output enable register to output buffer enable delay Setup time for bidirectional pins with PLL clock at LAB-adjacent input register Hold time for bidirectional pins with PLL clock at LAB-adjacent input register Condition C1 = 35 pF Clock-to-output delay for bidirectional pins with PLL clock at IOE register C1 = 35 pF Synchronous output enable register to output buffer disable delay with PLL Synchronous output enable register to output buffer enable delay with PLL C1 = 35 pF C1 = 35 pF Note to Tables 10-21 and 10-22: (1) These timing parameters are sample-tested only. Tables 10-23 and 10-24 show the external timing parameters for HC20K1500 devices. Table 10-23. HC20K1500 External Timing Parameters Symbol tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL Note (1) Unit ns ns Min 2.0 0.0 2.0 3.3 0.0 0.5 Max 5.0 ns ns ns 2.1 ns Table 10-24. HC20K1500 External Bidirectional Timing Parameters (Part 1 of 2) Note (1) Symbol tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL 3.9 Min 1.9 0.0 2.0 Max Unit ns ns 5.0 7.1 7.1 ns ns ns ns 10-14 Altera Corporation September 2008 Document Revision History Table 10-24. HC20K1500 External Bidirectional Timing Parameters (Part 2 of 2) Note (1) Symbol tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL Note to Tables 10-23 and 10-24: (1) Timing information is preliminary. Final timing information will be available in a future version of this data sheet. Min 0.0 0.5 Max Unit ns 2.1 4.2 4.2 ns ns ns Document Revision History Table 10-25 shows the revision history for this chapter. Table 10-25. Document Revision History Date and Document Version September 2008, v2.3 June 2007, v2.2 December 2006 v2.1 March 2006 January 2005 v2.0 June 2003 v1.0 Changes Made Updated chapter number and metadata. Minor text edits. Updated revision history. Formerly chapter 12; no content change. Update device names and other minor textual changes. Initial release of Operating Conditions, in the HardCopy Device Handbook Summary of Changes -- -- -- -- -- -- Altera Corporation September 2008 10-15 HardCopy Series Handbook, Volume 1 10-16 Altera Corporation September 2008 |
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